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ds05-10169-4e fujitsu semiconductor data sheet memory cmos 2 m 8 bits fast page mode dynamic ram mb81v17800a-60/60l/-70/70l cmos 2,097,152 8 bits fast page mode dynamic ram n description the fujitsu mb81v17800a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 8-bit increments. the mb81v17800a features a ?ast page mode of operation whereby high- speed random access of up to 1,024-bits of data within the same row can be selected. the mb81v17800a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb81v17800a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb81v17800a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb81v17800a are not critical and all inputs are lvttl compatible. n product line & features parameter mb81v17800a -60 -60l -70 -70l ras access time 60 ns max. 70 ns max. random cycle time 110 ns min. 130 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 432 mw max. 396 mw max. standby current lvttl level 3.6 mw max. 3.6 mw max. 3.6 mw max. 3.6 mw max. cmos level 1.8 mw max. 0.54 mw max. 1.8 mw max. 0.54 mw max. 2,097,152 words 8 bits organization silicon gate, cmos, advanced capacitor cell all input and output are lvttl compatible 2,048 refresh cycles every 32.8 ms self refresh function standard and low power versions early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb81v17800a-60/60l/-70/70l n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +4.6 v voltage of v cc supply relative to v ss v cc ?.5 to +4.6 v power dissipation p d 1.0 w short circuit output current 50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c (lcc-28p-m07) plastic soj package package and ordering information ?28-pin plastic (400mil) soj, order as mb81v17800a- pj ?28-pin plastic (400mil) tsop-ii with normal bend leads, order as mb81v17800a- pftn, mb81v17800a- lpftn (low power) (fpt-28p-m14) plastic tsop package (normal bend)
3 mb81v17800a-60/60l/-70/70l n capacitance (t a = 25 c, f = 1mhz) parameter symbol max. unit input capacitance, a 0 to a 10 c in1 5pf input capacitance, ras , cas , we , oe c in2 5pf input/output capacitance, dq 1 to dq 8 c dq 7pf fig. 1 ?mb81v17800a dynamic ram - block diagram mode control write clock gen a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 a 10 a 9 a 0 ras cas clock gen #2 data in buffer we dq 1 to dq 8 oe v cc v ss data out buffer column decoder clock gen #1 sense ampl & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder row decoder substrate bias gen refresh address counter
4 mb81v17800a-60/60l/-70/70l n pin assignments and descriptions 28-pin tsop (top view) we oe designator function a 0 to a 10 address inputs row : a 0 to a 10 column : a 0 to a 9 refresh : a 0 to a 10 ras row address strobe cas column address strobe write enable output enable dq 1 to dq 8 data input/output v cc +3.3 volt power supply v ss circuit ground v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dq 1 dq 2 dq 3 dq 4 v ss v ss dq 8 dq 7 dq 6 dq 5 we ras a 10 a 0 a 1 a 2 a 3 v cc cas oe a 9 a 8 a 7 a 6 a 5 a 4 1 pin index v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dq 1 dq 2 dq 3 dq 4 v ss v ss dq 8 dq 7 dq 6 dq 5 we ras n.c. a 10 a 0 a 1 a 2 a 3 v cc cas oe a 9 a 8 a 7 a 6 a 5 a 4 1 pin index n.c. marking side 28-pin soj (top view)
5 mb81v17800a-60/60l/-70/70l n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix. since only eleven address bits (a 0 to a 10 ) are available, the row and column inputs are separately strobed by ras and cas as shown in figure 1. first, eleven row address bits are input on pins a 0 -through-a 10 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edge of ras and cas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways-an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 to dq 8 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write- enable signal. data output the three-state buffers are lvttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . the data remains valid until either cas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 1,024 8-bits can be accessed and, when multiple mb81v17800as are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 3.0 3.3 3.6 v 0 c to + 70 c v ss 000 input high voltage, all inputs *1 v ih 2.0 v cc +0.3 v input low voltage, all inputs* *1 v il ?.0 0.8 v
6 mb81v17800a-60/60l/-70/70l n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol condition value unit min. typ. max. std power low power output high voltage v oh i oh = ? ma 2.4 v output low voltage v ol i ol = +2 ma 0.4 0.4 input leakage current (any input) i i(l) 0 v v in 3.6 v; 3.0 v v cc 3.6 v; v ss = 0 v; all other pins under test = 0 v ?0 10 10 m a output leakage current i dq(l) 0 v v out 3.6 v; data out disabled ?0 10 10 operating current (average power supply current) *2 mb81v17800a -60/60l i cc1 ras & cas cycling; t rc = min ma mb81v17800a -70/70l standby current (power supply current) lvttl level i cc2 ras = cas = v ih ma cmos level ras = cas 3 v cc ?0.2 v m a refresh current #1 (average power supply current) *2 mb81v17800a -60/60l i cc3 cas = v ih , ras cycling; t rc = min ma mb81v17800a -70/70l fast page mode current *2 mb81v17800a -60/60l i cc4 ras = v il, cas cycling; t pc = min ma mb81v17800a -70/70l refresh current #2 (average power supply current) *2 mb81v17800a -60/60l i cc5 ras cycling; cas -before-ras ; t rc = min ma mb81v17800a -70/70l battery back up current (average power supply current) *2 mb81v17800a -60/70 i cc6 ras cycling; cas -before-ras ; t rc = 16 m s t ras = min to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 1000 m a mb81v17800a -60l/70l ras cycling; cas -before-ras ; t rc = 62.5 m s t ras = min to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 300 refresh current #3 (average power supply current) mb81v17800a -60/60l i cc9 ras = v il , cas = v il self refresh; 1000 250 m a mb81v17800a -70/70l 120 120 110 110 1.0 1.0 500 150 120 120 110 110 120 120 110 110 120 120 110 110
7 mb81v17800a-60/60l/-70/70l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb81v17800a-60/60l mb81v17800a-70/70l unit min. max. min. max. 1 time between refresh std power t ref 32.8 32.8 ms low power 128 128 2 random read/write cycle time t rc 110 130 ns 3 read-modify-write cycle time t rwc 150 174 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?7ns 6 column address access time *8,9 t aa ?0?5ns 7 output hold time t oh 3?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time *10 t off ?5?7ns 10 transition time t t 350350ns 11 ras precharge time t rp 40?0ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 15?7ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time *11,12 t rcd 20 45 20 53 ns 16 cas pulse width t cas 15?7ns 17 cas hold time t csh 60?0ns 18 cas precharge time (normal) *19 t cpn 10?0ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 10?0ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 15?5ns 23 column address hold time from ras t ar 35?5ns 24 ras to column address delay time *13 t rad 15 30 15 35 ns 25 column address to ras lead time t ral 30?5ns 26 column address to cas lead time t cal 30?5ns 27 read command set up time t rcs 0?ns 28 read command hold time referenced to ras *14 t rrh 0?ns 29 read command hold time referenced to cas *14 t rch 0?ns 30 write command set up time *15,20 t wcs 0?ns 31 write command hold time t wch 15?5ns
8 mb81v17800a-60/60l/-70/70l n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb81v17800a-60/60l mb81v17800a-70/70l unit min. max. min. max. 32 write hold time from ras t wcr 35?5ns 33 we pulse width t wp 15?5ns 34 write command to ras lead time t rwl 15?7ns 35 write command to cas lead time t cwl 15?7ns 36 din set up time t ds 0?ns 37 din hold time t dh 15?5ns 38 data hold time from ras t dhr 35 35 ns 39 ras to we delay time *20 t rwd 80?2ns 40 cas to we delay time *20 t cwd 35?9ns 41 column address to we lead time *20 t awd 50?7ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before-ras refresh t csr 0?ns 44 cas hold time for cas -before-ras refresh t chr 10?2ns 45 access time from oe *9 t oea ?5?7ns 46 output buffer turn off delay from oe *10 t oez ?5?7ns 47 oe to ras lead time for valid data t oel 10?0ns 48 oe hold time referenced to we *16 t oeh 5?ns 49 oe to data in delay time t oed 15?7ns 50 cas to data in delay time t cdd 15?7ns 51 din to cas delay time *17 t dzc 0?ns 52 din to oe delay time *17 t dzo 0?ns 60 fast page mode ras pulse width t rasp 100000 100000 ns 61 fast page mode read/write cycle time t pc 40?5ns 62 fast page mode read-modify-write cycle time t prwc 80?9ns 63 access time from cas precharge *9,18 t cpa ?5?0ns 64 fast page mode cas precharge time t cp 10?0ns 65 fast page mode ras hold time from cas precharge t rhcp 35?0ns 66 fast page mode cas precharge to we delay time t cpwd 55?2ns
9 mb81v17800a-60/60l/-70/70l notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , cas = v ih and v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3 v. i cc6 is measured on condition that all address signals are ?ed steady state. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 5 ns. *5. input voltage levels are 0v and 3.0v, and input reference levels are v ih (min) and v il (max) for measuring timing of input signals. also, the transition time (t t ) is measured between v ih (min) and v il (max). the output reference levels are v oh = 2.0 v and v ol = 0.8 v. *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to two ttl loads and 100 pf. *10. t off and t oez is speci?d that output buffer change to high-impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min) + 2 t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satis?d for a read cycle. *15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satis?d. *18. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd, t rwd, t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state throughout the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations.
10 mb81v17800a-60/60l/-70/70l n functional truth table x: ? or ? * : it is impossible in fast page mode. operation mode clock input address input input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes.* t rcs 3 t rcs (min) write cycle (early write) l l l x valid valid valid high-z yes.* t wcs 3 t wcs (min) read-modify- write cycle llh ? ll ? h valid valid valid valid yes.* ras -only refresh cycle l h x x valid high-z yes. cas -before- ras refresh cycle l l x x high-z yes. t csr 3 t csr (min) hidden refresh cycle h ? llh ? x l valid yes. previous data is kept. fig. 2 ?t rac vs. t rcd fig. 4 ?t cpa vs. t cp fig. 3 ?t rac vs. t rad t rcd (ns) t rad (ns) t cp (ns) t rac (ns) t rac (ns) t cpa (ns) 60 40 100 80 120 20 060 40 100 80 60ns version 60 50 80 70 90 20 040 30 60 50 40 30 60 50 70 10 030 20 50 40 70ns version 60ns version 70ns version 60ns version 70ns version
11 mb81v17800a-60/60l/-70/70l ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) t rc t ras t ar t crp t csh t rcd t rsh t rp t cas t cdd t oel t ral t cal t cah t asc t rad t rah t asr t rcs t rrh t rch t oh t off t aa t cac t rac t dzc t on t oea t oez t oh t oed t on t dzo row add column add high-z a 0 to a 10 cas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) v ih v il oe description to implement a read operation, a valid address is latched in by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either cas or oe goes high, the output returns to a high-impedance state after t oh is satisfied. fig. 5 ?read cycle high-z
12 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be imple- mented in either of three ways ?early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl and t ral must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pin is latched with the falling edge of cas and written into memory. fig. 6 ?early write cycle (oe = ??or ?? t rc t ras t rp t crp t csh t rcd t rsh t cas t ar t asr t rah t asc t cah t wcr t wcs t wch t dhr t ds t dh row add column add high-z valid data in ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
13 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) description in the delayed write cycle, t wcs is not satisfied; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t ds ). fig. 7 ?delayed write cycle valid invalid data high-z high-z high-z data i n col add row add v ih v il oe t rc t ras t ar t csh t cas t rsh t rp t rcd t crp t asr t rah t asc t cah t rcs t wch t cwl t rwl t wp t ds t dh t dzc t on t oed t dzo t on t oez t oeh ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
14 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read-modify- write cycle, oe must be changed from low to high after the memory access time. fig. 8 ?read-modify-write cycle v ih v il oe row add col add valid data i n valid high-z t rwc t ras t ar t crp t rcd t rp t rad t asr t rah t asc t cah t rwd t rcs t awd t cwd t cwl t rwl t wp t dh t ds t dzc t oed t cac t aa t rac high-z t on t oea t oeh t oez t dzo t on t oh high-z ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) data
15 mb81v17800a-60/60l/-70/70l column address row add description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the lastest in occuring. ras cas we v ih v il dq (output) v oh v ol fig. 9 ?fast page mode read cycle t rasp t rhcp t rcd t rp t rsh t crp t rad t cas t csh t cp t cas t rah t cah t asc t asc t cah t cah t rrh t asc t ral t rcs t rch t rcs t rch t cdd t rcs t rch t on t aa t off t cac t dzc t aa t oh t oh t cac t off t dzc t cpa t oel t dzc t dzo t on t dzo t oez t oea t oez t oea t oed t oed dq (input) oe v ih v il col add valid data t asr a 0 to a 10 v ih v il high-z high-z high-z t pc t cas t dzo t oh t rac high-z ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) v ih v il v ih v il v ih v il column address
16 mb81v17800a-60/60l/-70/70l description the fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins is latched on the falling edge of cas and written into memory. during the fast page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. fig. 10 ?fast page mode early write cycle (oe = ??or ?? t cas t pc t csh t rasp t cas t cp t rsh t rp t cas t rcd t cah t asc t cah t ar t asc t cah t asc col row add add col add col add t wcs t wch t wcs t wch t wcr t wch t wcs t ds t dh t ds t dh t dh t ds t dhr valid data valid data valid data ras v ih v il cas v ih v il we v ih v il t rah t asr t crp a 0 to a 10 v ih v il dq (output) v oh v ol dq (input) v ih v il high-z ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
17 mb81v17800a-60/60l/-70/70l description the fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 11 ?fast page mode delayed write cycle t asc ras v ih v il cas v ih v il t rasp t csh t rcd t pc t rp t rsh t cas t cah t cwl t asc t cah t cas t ar t cp t rah t rcs t cwl t oeh t wp t ds t dh t dzc t on t oed t oeh t on t oed t ds t wp t rwl t dh t oez t oez t on t dzo t on t asr t cpr valid data we v ih v il a 0 to a 11 v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il t wch t wch high-z valid data ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) valid data row address column address col add
18 mb81v17800a-60/60l/-70/70l t oea description during the fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. fig. 12 ?fast page mode read-modify-write cycle t asc ras v ih v il cas v ih v il we v ih v il t rasp t rcd t rp t rwl t cwd t cah t asc t cah t cwd t rad t cp t rah t rcs t oeh t wcl t ds t dh t oed t ds t wp t wcl t dh t oez t oez t on t on t asr t crp t awd t wp t rcs t cpwd t dzc t rwd t cac t aa t on t oed t cac t aa t on t ras t oeh t oea t cpa oe v ih v il a 0 to a 11 v ih v il dq (output) v oh v ol dq (input) v ih v il t dzo high-z valid data ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) valid data valid data row address column address col add t rpwc
19 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v oh v ol ras v ih v il v ih v il dq (output) fig. 13 ?ras -only refresh (we = oe = ??or ?? high-z row address t rc t ras t rp t rpc t rah t asr t crp t crp t off t oh description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, d out pins are kept in a high-impedance state. cas v oh v ol ras v ih v il v ih v il dq (output) fig. 14 ?cas -before-ras refresh (addresses = we = oe = ??or ?? description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep- aration for the next cas -before-ras refresh operation. high-z t rc t ras t rp t rpc t chr t csr t cpn t off t oh ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq) ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
20 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v oh v ol ras v ih v il v ih v il dq (output) fig. 15 ?hidden refresh cycle description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. we v ih v il oe v ih v il v ih v il dq (input) t rc t rc t ras t rp t ras t oel t rp t crp t chr t rsh t rcd t rad t rah t asr t asc t ral t ar t cah t rcs t rrh t cdd t aa t rac t cac t dzc t on t dzo t oea t oez t oed t off t oh high-z valid data out row address column address high-z ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
21 mb81v17800a-60/60l/-70/70l a 0 to a 10 cas v ih v il v oh v ol ras v ih v il v ih v il dq (output) fig. 16 ?cas -before-ras refresh counter test cycle we v ih v il oe v ih v il v ih v il dq (input) t crp column addresses high-z high-z valid data in high-z t rcd t cp t frsh t fcas t rp t fcah t asc t rcs t cwl t rwl t fcwd t fcac t ds t dzc t wp t dh t oed t dzo t oeh t on t oez description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are defined as follows: row address: bits a 0 through a 10 are defined by the on-chip refresh counter. column address: bits a 0 through a 9 are defined by latching levels on a 0 to a 9 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ??to all 2,048 row addresses at the same column address by using normal write cycles. 4) read ??written in procedure 3) and check; simultaneously write ??to the same addresses by using cas - before-ras refresh counter test (read-modify-write cycles). repeat this procedure 2,048 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 2,048 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). mb81v17800a-70/70l mb81v17800a-60/60l unit parameter min . max. ns no . min. max. 90 55 50 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay time 91 35 ns 35 column address hold time cas pulse width 77 ns 70 99 ns 90 ns 90 99 access time from cas t fcac t fcah t fcwd t fcas t frsh ras hold time 92 93 94 note: assumes that cas -before-ras refresh counter test cycle only. t oea valid data ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
22 mb81v17800a-60/60l/-70/70l cas v oh v ol ras v ih v il v ih v il dq (output) fig. 17 ?self refresh cycle (a 0 to a 10 = we = oe = ??or ?? description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter. if cas goes to ??before ras goes to ??(cbr) and the condition of cas ??and ras ??is kept for term of t rass (more than 100 m s), the device can enter the self refresh cycle. following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during ?as = l?and ?as = l? exit from self refresh cycle is performed by togging ras and cas to ??with specified t chs min. in this time, ras must be kept ? with specified t rps min. using self refresh mode, data can be retained without external cas signal during system is in standby. restriction for self refresh operation; for self refresh operation, the notice below must be considered. 1) in the case that distributed cbr refresh are operated between read/write cycles self refresh cycles can be executed without special rule if 2,048 cycles of distributed cbr refresh are executed within t ref max. 2) in the case that burst cbr refresh or distributed burst ras -only refresh are operated between read/write cycles 2,048 times of burst cbr refresh or 2,048 times of burst ras -only refresh must be executed before and after self refresh cycles. high-z t oh t off t cpn t csr t rass t rps t rpc t chs ras v ih v il * read/write operation can be performed non refresh time within t ns or t sn read/write operation self refresh operation read/write operation t rass t ns < 2 ms t sn < 2 ms 2,048 burst refresh cycle 2,048 burst refresh cycle * mb81v17800a-70/70l mb81v17800a-60/60l unit parameter min . max. m s no . min. max. 100 symbol (at recommended operating conditions unless otherwise noted.) ras precharge time 101 125 ns 110 ras pulse width cas hold time ?0 ns ?0 t rass t rps t chs 100 102 note: assumes self refresh cycle only. 100 ??or ??level (excluding address and dq) ??or ??level, ?? ? ??or ?? ? ??transition (address and dq)
23 mb81v17800a-60/60l/-70/70l n package dimensions 28-lead plastic leaded chip carrier (case no.: lcc-28p-m07) C.001 +.002 C0.02 +0.05 C.008 +.014 C0.20 +0.35 * 18.420.13(.725.005) .008 0.20 .134 3.40 (.370.020) 9.400.51 2.75(.108)nom 0.64(.025)min r0.81(.032)typ 0.81(.032)max 0.430.10(.017.004) details of "a" part 2.50(.098)nom 0.10(.004) (.432.005) 10.970.13 (.400) nom 10.16 1 28 15 14 (.050.005) 1.270.13 16.51(.650)ref index "a" lead no *: resin protrusion. (each side: .006 (0.15) max) ? 1994 fujitsu limited c28058s-2c dimensions in mm (inches)
24 mb81v17800a-60/60l/-70/70l n package dimensions 28-lead plastic flat package (case no.: fpt-28p-m14) lead no. "a" 0.15(.006) max 0.50(.020) max 0.15(.006) 0.25(.010) details of "a" part (.005.002) 0.1250.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.400.004) 10.160.10 (.463.008) 11.760.20 (stand off) 0.05(.002)min 1.150.05(.045.002) 0.10(.004) typ. 1.27(.050) ref. 16.51(.650) * 0.21(.008) m (.016.004) 0.400.10 (.725.004) 18.410.10 index 14 1 15 28 1994 fujitsu limited f28040s-2c-1 c dimensions in mm (inches) *: resin protrusion. (each side: .006 (0.15) max)
25 mb81v17800a-60/60l/-70/70l all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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